1. Field of the Invention
The present invention relates to a semiconductor device with a large current capacity and a high breakdown voltage, such as a metal-oxide semiconductor field-effect transistor (MOSFET), an IGBT, a bipolar transistor, and semiconductor diode, and also the present invention relates to a method for fabricating the semiconductor device mentioned above.
2. Description of Prior Art
In general, structures of the semiconductor elements can be roughly grouped into two types: a lateral structure having an electric contact portion on one side thereof; and a vertical structure having electric contact portions on both sides thereof.
One example of a semiconductor element with the lateral structure is a SOI (silicon on insulator)xe2x80x94MOSFET (metal oxide silicon field effect transistor) shown in FIG. 1A and FIG. 1B, in which FIG. 1A is a plan view of the semiconductor element, while FIG. 1B is a cross-sectional view of the semiconductor along a line 1B-1Bxe2x80x2 in FIG. 1A.
A structure of the SOI-MOSFET is based on an offset gate structure of an n-channel MOSFET, in which a p-type channel diffusion layer 7, an n+-type low doped drain region (drain/drift region) 90, and an n+-type drain region 9 are formed on a semiconductor base plate 5 via an insulation membrane 6 in that order. In addition, an n+-type source region 8 is formed on a part of a surface of the p-type channel diffusion layer 7, and also an insulation layer 12 is formed on a region extending from an end portion of the region 8 to an end of the n+-type drain region 9. Particularly, in close proximity to the above n+-type source region 8, the insulating film 12 has a remainder portion 10 which is thinner than the rest of the insulating film and is positioned on the boundary of the p-type channel diffusion layer 7 and the n+-type low doped drain region 90. A gate electrode 11 is formed so as to cover the insulation film 12 from its thin portion 10 to its thick portion.
The low doped drain region 90 can be operated as a drift region for transferring carriers due to the effect of an electrical field if the MOSFET is in the ON mode. If the low doped drain region 90 is in the OFF mode, on the other hand, it becomes a depletion region to reduce an electric field strength applied thereon, resulting in an increase in breakdown voltage. It is possible to reduce the drift resistance of the low doped drain region 90 by increasing the concentration of impurities in the low doped drain region 90 and by decreasing electricity flowing through the region 90. As a result, a substantial ON resistance (drain-source resistance) of the MOSFET can be lowered. In this case, however, it will be difficult to extend the boundaries of the depletion layer between the drain and the channel to be developed from a p-n junction between the p-type channel diffusion layer 7 and the n-type low doped drain region 90, so that the maximum permissible (critical) electric field strength of silicon is reached at an earlier time, resulting in a reduction in the breakdown voltage (drain-source voltage). Hence, a trade-off relationship exists between the ON resistance (current capacity) and the breakdown voltage. Similarly, it has been known that the semiconductors such as IGBT, bipolar transistors, and semiconductor diodes make the above trade-off relationship.
Referring now to FIGS. 2A and 2B, another example of the conventional MOSFETs having a lateral structure will be described in detail, in which FIG. 2A is a cross-sectional view of a p-channel MOSFET and FIG. 2B is a cross-sectional view of a double diffusion type n-channel MOSFET.
The p-channel MOSFET shown in FIG. 2A comprises a n-type channel diffusion layer 3 formed on a p-type semiconductor layer 4, a gate electrode 11 with a field plate formed on the diffusion layer 3 via a gate insulation film 10, a p+-type source region 18 formed on a part of the diffusion layer 3 in close proximity to one end of the gate electrode 11, a p-type low doped drain region (drain/drift region) 14 formed as a well having an end immediately underneath the other end of the gate electrode 11, a n+-type contact region 71 adjacent to the p+-type source region 18, a thick insulation film 12 formed on the p-type low doped drain region 14. In this structure, therefore, its ON resistance and breakdown voltage can be defined as the trade-off relationship based on the amount of electricity flowing through the well-shaped p-type low doped drain region 14 and the concentration of its impurities.
The double diffusion type n-channel MOSFET shown in FIG. 2B comprises a n-type low doped drain layer (drain/drift layer) 22 formed on a p-type semiconductor layer 4, a gate electrode 11 with a field plate formed on the low doped drain layer 22 via a gate insulation film 10, a p-type channel diffusion region 17 formed on a part of the low doped drain layer 22 in close proximity to one end of the gate electrode 11, n+-type source region 8 formed as a well in the p-type channel diffusion region 17, an n+-type drain region 9 formed as a well positioned at a distance from the n+-type source region 8 and the gate electrode 11, a well-shaped p-type top layer 24 formed on a surface layer between the gate electrode 11 and the n+-type drain region 9, a p+-type contact region 72 adjacent to the n+-type source region 8, and a thick insulation film 12 formed on the p-type top layer 24. In this structure, therefore, its ON resistance and breakdown voltage can be defined as the trade-off relationship based on the amount of electricity flowing through the well-shaped n-type low doped drain region 22 and the concentration of its impurities.
In the structure of FIG. 2B, however, the n-type low doped drain layer 22 is sandwiched between the p-type semiconductor layer 4 and the p-type top layer 24, so that it can be provided as the structure with a high breakdown voltage if the MOSFET is in the OFF mode because the low doped drain layer 22 is depleted at an earlier time by widening a depletion layer not only from the p-n junctions ja with the p-type channel diffusion region 17 but also from p-n junctions jb of upper and lower sides of the n-type low doped drain layer 22 while the concentration of impurities in the low doped drain layer 22 can be increased.
FIG. 3 shows a trench gate type n-channel MOSFET as an example of the vertical semiconductor element. The n-channel MOSFET comprises a n-type low doped drain layer 39 formed on a n+-type drain layer 29 electrically contacted with a back electrode (not shown), a trench gate electrode 21 imbedded in a trench formed on a surface of the low doped drain layer 39 via a gate insulation film 10, a p-type channel diffusion layer 27 formed on a surface of the low doped drain layer 39 at a relatively shallow depth compared with that of the trench gate electrode 21, a n+-type source region 18 formed along an upper edge of the trench gate electrode 21, and a thick insulation film 12 as a sheathing of the gate electrode 21. By the way, it is possible to make a n-type IGBT structure using a double structure made of a n+-type upper layer and a p+-type under layer instead of the single layered n+-drain layer 29. In this kind of the vertical structure, therefore, the low doped drain layer 39 acts as a drift region for drift current flowing in the vertical direction if the MOSFET is in the ON mode, while it is depleted to increase its breakdown voltage if the MOSFET is in the OFF mode. In this case, its ON resistance and breakdown voltage can be defined as the trade-off relationship on the basis of a thickness of the low doped drain layer 39 and the concentration of its impurities.
FIG. 4 is a graph that shows the relationship between an ideal breakdown voltage and an ideal ON resistance of the silicon n-channel MOSFET. In this figure, it is based on the hypothesis that the breakdown voltage cannot be lowered by changing its form and that the ideal ON resistance is small enough to ignore electrical resistance of the regions except the low doped drain region.
In FIG. 4, the line A represents the relationship between an ideal breakdown voltage and an ideal ON resistance of the vertical structure type n-channel MOSFET of FIG. 3; the line B represents the relationship between an ideal breakdown voltage and an ideal ON resistance of a n-channel type MOSFET like the MOSFET of FIG. 2A where the p-channel type is replaced by an n-channel type; the line D represents the relationship between an ideal breakdown voltage and an ideal ON resistance of the vertically structured double diffused n-channel MOSFET of FIG. 2B; and the line C represents the relationship between an ideal breakdown voltage and an ideal ON resistance of the n-channel MOSFET of FIG. 11.
The vertical n-channel MOSFET is constructed so as to match the direction of the drift current flowing in the ON mode and the direction of expanding the depletion layer caused by a reverse bias in the OFF mode. For the low doped drain layer 39 of FIG. 3, an approximation of the breakdown voltage BV at the time of the OFF mode can be obtained by the following equation:
BV=Ec2{dot over (a)}o{dot over (a)}sixc3xa1(2xe2x88x92xc3xa1)/2qNDxe2x80x83xe2x80x83(1)
wherein
Ec is Ec (ND) which is the maximum electric field strength of silicon at the impurity concentration of ND;
{dot over (a)}o is a dielectric constant in a vacuum;
{dot over (a)}si is a relative dielectric constant of silicon;
q is a unit charge;
ND is the impurity concentration of the low doped region; and xc3xa1 is a factor (0 less than xc3xa1 less than 1).
In addition, the ideal ON resistance per unit area in the ON mode can be approximately obtained by the following equation:
R=xc3xa1W/ìqND
wherein
ì is ì (ND) which is electron mobility at the impurity concentration of ND; and
W is equal to Ec{dot over (a)}o{dot over (a)}si/q ND.
Therefore, R can be represented by the following formula:
R=Ec{dot over (a)}o{dot over (a)}sixc3xa1/ìq2ND2.xe2x80x83xe2x80x83(2)
Thus, if qND is removed from the formula (2) using the formula (1) and if an optimum value such as ⅔ is chosen for xc3xa1, the following formula results:
R=BV2(27/8Ec3{dot over (a)}o{dot over (a)}siì)xe2x80x83xe2x80x83(3)
In this formula, the ON resistance R seems to be proportional to the square of the breakdown voltage BV. In this case, however, the line A of FIG. 4 is roughly proportional to BV raised to the 2.4th to 2.6th power.
In the case of the n-channel type MOSFET structure where the channel type of the MOSFET of FIG. 2A is replaced, the drift current flows in the lateral direction if it is in the ON mode, while the depletion layer spreads upward (in the vertical direction) from the bottom of the well substantially faster than spreading from one end of the well in the lateral direction. For obtaining a higher breakdown voltage in the depletion layer spreading out in the vertical direction, it should be depleted from a boundary surface of the p-n junction (i.e., the bottom of the well) between the low doped drain region 14 and the channel diffusion layer 3 to a surface of the low doped drain region 14 (i.e., the surface of the well), so that the maximum value of the net doping amount in the low doped drain region 14 can be restricted by the following formula:
SD=Ec{dot over (a)}o{dot over (a)}si/qxe2x80x83xe2x80x83(4)
If the length of the low doped drain region 14 is defined as L, an ideal breakdown voltage BV is represented by the formula:
BV=Ec Lxc3xa2xe2x80x83xe2x80x83(5)
wherein
xc3xa2 is a factor (0 less than xc3xa2 less than 1)
In addition, the ideal ON resistance R per unit area in the ON mode can be approximately obtained by the following equation:
R=L2/ìqSDxe2x80x83xe2x80x83(6)
wherein
ì is ì (SD) which is electron mobility at the maximum impurity concentration of SD. Thus, if L is removed from the formula (6) by substituting the formulae (4) and (5), the following formula results:
R=BV2/xc3xa22Ec3{dot over (a)}o{dot over (a)}siìxe2x80x83xe2x80x83(7)
In the case of the vertically structured double diffusion type n-channel MOSFET shown in FIG. 2B, it is constructed by forming a p-type top layer 24 on the MOSFET structure of FIG. 2A. Therefore, the depletion layer spreads in the vertical direction, and thus the low doped drain layer 22 can be depleted quickly. As shown in the following formula (8), the net doping amount SD in the low doped region 22 can be increased twice as much as that of FIG. 2A.
SD=2Ec{dot over (a)}o{dot over (a)}si/qxe2x80x83xe2x80x83(8)
In this case, the relationship between an ideal ON resistance R and an ideal breakdown voltage of the above structure is represented by the formula:
R=BV2/2xc3xa22EC3{dot over (a)}o{dot over (a)}siìxe2x80x83xe2x80x83(9)
As is evident from a comparison between the above formula (7) and the above formula (9), the trade-off relationship (line B in FIG. 4) between the ON resistance and the breakdown voltage of the vertically structured n-channel type MOSFET of FIG. 2B is slightly improved over the trade-off relationship (line C in FIG. 4) between the ON resistance and the breakdown voltage of the n-channel type MOSFET where the channel type of the MOSFET of FIG. 2A is replaced. In this case, however, the improvement only permits the doping concentration twice as much as before and it does not provide flexibility in a design criterion of the current capacity and the breakdown voltage of the semiconductor.
Accordingly, it is an object of the present invention to provide a semiconductor device which relaxes the relationship between the ON resistance and the breakdown voltage to enable an increase in the current capacity by a reduction in the ON resistance under the high breakdown voltage.
It is another object of the present invention to provide a manufacturing method for rolling out semiconductor devices.
In a first aspect of present invention, there is provided a semiconductor device having a drift region where a drift current flows if it is in an ON mode and which is depleted if it is in an OFF mode, wherein
the drift region is formed as a structure having a plurality of first conductive type divided drift path regions which are connected together in parallel to form a group of parallel drift paths and a plurality of second conductive type side regions, in which each of the second conductive type side regions is positioned between adjacent the first conductive type divided drift path regions to form p-n junctions.
Here, the semiconductor device may further comprise:
at least one additional second side region which is connected to an outer side of a first conductive type divided drift path region positioned at an outer side of the group of parallel drift paths.
In a second aspect of present invention, there is provided a semiconductor device having a drift region where a drift current flows if it is in an ON mode and which is depleted if it is in an OFF mode, and the drift current flows in a lateral direction and the drift region is formed on a semiconductor or an insulation film on the semiconductor, wherein
the drift region is formed as a parallel stripe structure in which a plurality of stripe-shaped first conductive divided drift path regions and a plurality of stripe-shaped second conductive type compartment regions are alternatively arranged on a plane one by one in parallel.
In a third aspect of present invention, there is provided a semiconductor device having a drift region where a drift current flows if it is in an ON mode and which is depleted if it is in an OFF mode, and the drift current flows in a lateral direction and the drift region is formed on a semiconductor or an insulation film on the semiconductor, wherein
the drift region is formed as a parallel stacked structure in which a plurality of layer-shaped first conductive divided drift path regions and a plurality of layer-shaped second conductive type compartment regions are alternatively stacked on a plane one by one in parallel.
In a fourth aspect of present invention, there is provided a semiconductor device having a drift region where a drift current flows if it is in an ON mode and which is depleted if it is in an OFF mode, and the drift current flows in a lateral direction and the drift region is formed on a second conductive type semiconductor, wherein
the drift region comprises:
a first conductive type divided drift region formed on the second conductive type semiconductor layer;
a well-shaped second conductive type compartment region formed on the first conductive type divided drift path region; and
a secondary first conductive type divided drift path region formed on a surface layer of the well-shaped second conductive type compartment region and connected to the first conductive type divided drift path region in parallel.
In a fifth aspect of present invention, there is provided a semiconductor device having a drift region where a drift current flows if it is in an ON mode and which is depleted if it is in an OFF mode, and the drift current flows in a vertical direction and the drift region is formed on a semiconductor, wherein
the drift region comprises a plurality of first conductive type divided drift regions in which each of them has a layer structure along the vertical direction and a plurality of first conductive type compartment regions in which each of them has a layer structure along the vertical direction, and
the plurality of first conductive type divided drift regions and the plurality of first conductive type compartment regions are stacked one by one in parallel in a direction perpendicular to the vertical direction to form a laterally stacked parallel structure.
In a sixth aspect of present invention, there is provided a method of manufacturing a semiconductor device having a drift region where a drift current flows if it is in an ON mode and which is depleted if it is in an OFF mode, and the drift current flows in a lateral direction and the drift region is formed on a second conductive type semiconductor, where the drift region has: a first conductive type divided drift region formed on the second conductive type semiconductor layer; a well-shaped second conductive type compartment region formed on the first conductive type divided drift path region; and a secondary first conductive type divided drift path region formed on a surface layer of the well-shaped second conductive type compartment region and connected to the first conductive type divided drift path region in parallel, comprising steps of:
forming a first conductive type divided drift path region on a second conductive type semiconductor layer made of silicon by a thermal diffusion after performing a phosphorus ion-implantation;
forming an well-shaped second conductive type compartment region on the first conductive type divided drift region by a thermal diffusion after performing a selective boron ion-implantation; and
thermally oxidizing a structure obtained by the selective boron ion-implantation to form a secondary first conductive type divided drift path region on a surface thereof through use of a concentration of phosphorus ions which are unevenly distributed on a surface of the silicon and a dilution of boron ions which are unevenly distributed into an oxidized film.